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| products and specifications discussed herein ar e subject to change by micron without notice. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm features pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_1.fm - rev. a 8/05 en 1 ?2003, 2004, 2005 micron technology, inc. all rights reserved. ddr sdram vlp registered dimm mt18vdvf6472d ? 512mb MT18VDVF12872D ? 1gb for the latest data sheet, refer to micron?s web site: www.micron.com/products/modules features ? 184-pin, very low profile dual in-line memory module (vlp dimm) ? fast data transfer rates: pc2100 or pc2700 ? utilizes 266 mt/s and 333 mt/s ddr sdram components ? registered inputs with one-clock delay ? phase-lock loop (pll) clock driver to reduce loading ? supports ecc error detection and correction ? 512mb (64 meg x 72) and 1gb (128 meg x 72) ?v dd = v ddq = +2.5v ?v ddspd = +2.3v to +3.6v ? 2.5v i/o (sstl_2 compatible) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? bidirectional data strobe (dqs) transmitted/ received with data?i.e., source-synchronous data capture ? differential clock inputs ck and ck# ? four internal device banks for concurrent operation ? programmable burst lengths: 2, 4, or 8 ? auto precharge option ? auto refresh and self refresh modes ? 7.8125s maximum averag e periodic refresh interval ? serial presence detect (spd) with eeprom ? programmable read cas latency ? gold edge contacts ?dual rank figure 1: 184-pin vlp dimm (mo-206) notes:1. contact micron for product availability. 2. cl = cas (read) latency; registered mode adds one clock cycle to cl. options marking ?package 184-pin dimm (standard) g 184-pin dimm (lead-free) 1 y ? memory clock, speed, cas latency 2 6ns (166mhz), 333 mt/s, cl = 2.5 -335 7.5ns (133 mhz), 266 mt/s, cl = 2 -262 1 7.5ns (133 mhz), 266 mt/s, cl = 2 -26a 1 7.5ns (133 mhz), 266 mt/s, cl = 2.5 -265 ?pcb height very low-profile 0.72in (18.29mm) 1 very low profile hei g ht 0.72in (18.29mm)
pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_1.fm - rev. a 8/05 en 2 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm features note: all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory fo r current revision codes. example: mt18vdvf6472dy-265b1 . table 1: address table 512mb 1gb refresh count 8k 8k row addressing 8k (a0?a12) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) device configuration 256mb (32 meg x 8) 512mb (64 meg x 8) column addressing 1k (a0?a9) 2k (a0?a9, a11) module rank addressing 2 (s0#, s1#) 2 (s0#, s1#) table 2: part numbers and timing parameters part number module density configuration module bandwidth memory clock/ data rate latency (cl - t rcd - t rp) mt18vdvf6472dg-335__ 512mb 64 meg x 72 2.7 gb /s 6ns/333 mt/s 2.5-3-3 mt18vdvf6472dy-335__ 512mb 64 meg x 72 2.7 gb /s 6ns/333 mt/s 2.5-3-3 mt18vdvf6472dg-262__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt18vdvf6472dy-262__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt18vdvf6472dg-26a__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt18vdvf6472dy-26a__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt18vdvf6472dg-265__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt18vdvf6472dy-265__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt18vdvf6472dg-202__ 512mb 64 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt18vdvf6472dy-202__ 512mb 64 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 MT18VDVF12872Dg-335__ 1gb 128 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 MT18VDVF12872Dy-335__ 1gb 128 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 MT18VDVF12872Dg-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 MT18VDVF12872Dy-262__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 MT18VDVF12872Dg-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 MT18VDVF12872Dy-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 MT18VDVF12872Dg-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 MT18VDVF12872Dy-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 MT18VDVF12872Dg-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 MT18VDVF12872Dy-202__ 1gb 128 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72dtoc.fm - rev. a 8/05 en 3 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pin assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 pll and register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 serial presence-detect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 dll enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 register and pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 temperature and air flow specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 serial presence-detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 spd clock and data conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 spd start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 spd stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 spd acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 module dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72dlof.fm - rev. a 8/05 en 4 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm list of figures list of figures figure 1: 184-pin vlp dimm (mo-206) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: pin locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: very low profile dimm functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: mode register definition diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: cas latency diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6: extended mode register definition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: derating da ta valid window ( t qh - t dqsq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8: pull-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 9: pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 10: initialization flow di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 11: component case temperature vs. air flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 12: data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 13: definition of start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 14: acknowledge response from receiv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 15: spd eeprom timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 16: 184-pin vlp rdimm dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72dlot.fm - rev. a 8/05 en 5 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 2: part numbers and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5: burst definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: cas latency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: commands truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8: dm operation truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 9: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 10: ac input operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11: i dd specifications and conditions ? 512mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 12: i dd specifications and conditions ? 1gb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 13: capacitance (512mb only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 14: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .20 table 15: register timing requirements and switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 16: pll clock driver timing requirements and switching ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . .30 table 17: eeprom device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 18: eeprom operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 19: serial presence-detect eeprom dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 20: serial presence-detect eeprom ac op erating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 21: serial presence-detect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 6 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm pin assignments and descriptions pin assignments and descriptions figure 2: pin locations table 3: pin assignment 184-pin dimm front 184-pin dimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dqs8 70 v dd 93 v ss 116 v ss 139 v ss 162 dq47 2dq0 25 dqs2 48 a0 71 nc 94 dq4 117 dq21 140 dm8 163 nc 3v ss 26 v ss 49 cb2 72 dq48 95 dq5 118 a11 141 a10 164 v dd q 4dq1 27 a9 50 v ss 73 dq49 96 v dd q119 dm2 142 cb6 165 dq52 5dqs0 28 dq18 51 cb3 74 v ss 97 dm0 120 v dd 143 v dd q 166 dq53 6dq2 29 a7 52 ba1 75 dnu 98 dq6 121 dq22 144 cb7 167 nc 7v dd 30 v dd q 53 dq32 76 dnu 99 dq7 122 a8 145 v ss 168 v dd 8 dq3 31 dq19 54 v dd q77v ddq 100 v ss 123 dq23 146 dq36 169 dm6 9nc 32 a5 55 dq33 78 dqs6 101 nc 124 v ss 147 dq37 170 dq54 10 reset# 33 dq24 56 dqs4 79 dq50 102 nc 125 a6 148 v dd 171 dq55 11 v ss 34 v ss 57 dq34 80 dq51 103 nc 126 dq28 149 dm4 172 v dd q 12 dq8 35 dq25 58 v ss 81 v ss 104 v dd q 127 dq29 150 dq38 173 nc 13 dq9 36 dqs3 59 ba0 82 nc 105 dq12 128 v dd q 151 dq39 174 dq60 14 dqs1 37 a4 60 dq35 83 dq56 106 dq13 129 dm3 152 v ss 175 dq61 15 v dd q38 v dd 61 dq40 84 dq57 107 dm1 130 a3 153 dq44 176 v ss 16 dnu 39 dq26 62 v dd q85 v dd 108 v dd 131 dq30 154 ras# 177 dm7 17 dnu 40 dq27 63 we# 86 dqs7 109 dq14 132 v ss 155 dq45 178 dq62 18 v ss 41 a2 64 dq41 87 dq58 110 dq15 133 dq31 156 v dd q 179 dq63 19 dq10 42 v ss 65 cas# 88 dq59 111 cke1 134 cb4 157 s0# 180 v dd q 20 dq11 43 a1 66 v ss 89 v ss 112 v dd q 135 cb5 158 s1# 181 sa0 21 cke0 44 cb0 67 dqs5 90 dnu 113 nc 136 v dd q 159 dm5 182 sa1 22 v dd q 45 cb1 68 dq42 91 sda 114 dq20 137 ck0 160 v ss 183 sa2 23 dq16 46 v dd 69 dq43 92 scl 115 a12 138 ck0# 161 dq46 184 v ddspd u11 u1 u2 u3 u4 u5 u 6 u7 u8 u9 u10 u11 u1 6 u17 u12 u13 u14 u15 u18 u19 u20 u21 u22 pin 93 pin 144 pin 145 pin 184 pin 1 pin 52 pin 53 pin 92 in d i c ates a v dd or v ddq pin in d i c ates a v ss pin front view ba c k view very low profile pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 7 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm pin assignments and descriptions table 4: pin descriptions pin numbers may not correlat e with symbols; refer to pin assignmen t tables on page 6 for more information pin numbers symbol type description 10 reset# input asynchronously forces all regi stered ouputs low when reset# is low. this signal can be used during power-up to ensure cke is low and dqs are high-z. 63, 65, 154 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 137, 138 ck0, ck0# input clock: ck, ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck,and negative edge of ck#. output data (dq and dqs) is referenced to th e crossings of ck and ck#. 21,111 cke0, cke1 input clock enable: cke high activate s and cke low deactivates the internal clock, input buffers an d output drivers. taking cke low provides precharge po wer-down and self refresh operations (all device banks idle), or active power-down (row active in any device bank). cke is synchronous for power-down entry and exit, an d for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintain ed high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an ss tl_2 input but will detect an lvcmos low level after v dd is applied. 157, 158 s0#, s1# input chip selects: s# enables (r egistered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 52, 59 ba0, ba1 input bank address: ba0 and ba1 defi ne to which device bank an active, read, write, or precharge command is being applied. 27, 29, 32, 37, 41, 43, 48, 115, 118, 122, 125, 130, 141 a0?a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determine s whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device bank s (a10 high). the address inputs also provide the op-code du ring a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode regi ster) is loaded during the load mode register command. 97, 107, 119, 129, 140, 149, 159, 169, 177 dm0?dm8 input data write mask: dm low allo ws write operation. dm high blocks write operation. dm state does not affect read command. 5, 14, 25, 36, 47, 56, 67, 78, 86 dqs0?dqs8 input/ output data strobe: output with read data, input with write data. dqs is edge-aligned with read data, centered in write data. used to capture data. 44, 45, 49, 51, 134, 135, 142, 144 cb0?cb7 input/ output check bits. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 8 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm pin assignments and descriptions 2, 4, 6, 8, 12,13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 dq0?dq63 input/ output data i/os: data bus. 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfe r to and from the module. 181, 182, 183 sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 91 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 1v ref supply sstl_2 reference voltage. 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v dd q supply dq power supply: +2.5v 0.2v. 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd supply power supply: +2.5v 0.2v. 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss supply ground. 184 v ddspd supply serial eeprom positive po wer supply: +2.3v to +3.6v. 16, 17, 75, 76, 90 dnu ? do not use: thes pins are not connected on these modules, but are assigned pins on other modules in this product family. 9, 71, 82, 101, 102, 103, 113, 115 (256mb), 163, 167, 173 nc ? no connect: these pins should be left unconnected. table 4: pin descriptions (continued) pin numbers may not correlat e with symbols; refer to pin assignmen t tables on page 6 for more information pin numbers symbol type description pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 9 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm functional block diagrams functional block diagrams unless otherwise noted, resistor values are 22 . per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/numberguide. standard modules use the following ddr sdram devices: mt46v 32m8fg (512mb) and mt46v64m8fg (1gb). lead-free modules us e the following ddr sdram devices: mt46v32m8bg (512mb) and mt46v64m8bg (1gb). figure 3: very low profile dimm functional block diagram a0 sa0 serial pd sda a1 sa1 a2 sa2 s0# s1# ba0, ba1 a0-a12 ras# cas# cke0 cke1 we# rs0#: ddr sdrams, rank 0 rs1#: ddr sdrams, rank 1 rba0, rba1: ddr sdrams ra0-ra12: ddr sdrams rras#: ddr sdrams rcas#: ddr sdrams rcke0: ddr sdrams, rank 0 rcke1: ddr sdrams, rank 1 rwe#: ddr sdrams ck ck# v ref v ss ddr sdrams u1-u5, u8- u15, u18-u22 ddr sdrams u1-u5, u8- u15, u18-u22 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u11 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u9 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u8 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 rs0# r e g i s t e r s wp pll ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 register x 2 scl u1 u21 u3 u15 rs1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm4 dqs4 dm1 dqs1 dm5 dqs5 u14 dm cs# dqs dm2 dqs2 dm6 dqs6 dm cs# dqs dm cs# dqs u10 u13 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm3 dqs3 dm7 dqs7 u19 dm cs# dqs u12 dm8 dqs8 u5 dm cs# dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v ddq v dd ddr sdrams u1-u5, u8- u15, u18-u22 ddr sdrams u1-u5, u8 -u15, u18-u22 ck0 ck0# 120 u6, u17 u7 u16 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq u22 u20 u18 module rank 0: u1-u5, u8-u11 module rank 1: u12-u15, u18-u22 120 dm cs# dqs v ddspd spd/eeprom reset# pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 10 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm general description general description the mt18vdvf6472d and MT18VDVF12872D are high-speed cmos, dynamic random- access, 512mb and 1gb memory modules orga nized in x72 (ecc) configuration. ddr sdram modules use internally config ured quad-bank ddr sdram devices. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram mo dule effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n - bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr sdram modules are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. th e address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select devices bank; a0?a12 select device row). the address bits registered coinci- dent with the read or write command are used to select the device bank and starting device column location for the burst access. ddr sdram modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and acti- vation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are compatible with the jedec standa rd for sstl_2. all outputs are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 256mb or 512mb ddr sdram component data sheets. pll and register operation ddr sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the ri sing clock edge and sent to the ddr sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr sdram devices. the re gisters and pll minimize system and clock loading. serial presence-detect operation ddr sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage de vice contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 11 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm mode register definition various sdram organizations and timing parameters. the remaining 128 bytes of stor- age are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (dat a) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. wr ite protect (wp) is tied to ground on the module, permanently disabling hardware write protect. mode register definition the mode register is used to define the specific mode of operation of ddr sdram devices. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 4, "mode register definition dia- gram," on page 12. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress , and the controller must wait the specified time before initiating the subs equent operation. violating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst le ngth, a3 specifies the type of burst (sequen- tial or interleaved), a4?a6 specify the cas latency, and a7?a12 specify the operating mode. burst length read and write accesses to ddr sdram devices are burst oriented, with the burst length being programmable, as shown in figure 4, "mode register definition diagram," on page 12. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a1?a i when the burst length is set to two, by a2?a i when the burst length is set to four and by a3?a i when the burst length is set to eight (where a i is the most significant column address bit for a given configuration. see note 5 of table 5, "burst definition table," on page 13, for a i values). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the pro- grammed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as show n in table 5, "burst definition table," on page 13. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 12 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm mode register definition read latency the read latency is the delay, in clock cycles, between the registration of a read com- mand and the availability of the first bit of ou tput data. the latency can be set to 2 or 2.5 clocks, as shown in figure 5, "cas latency diagram," on page 14. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . figure 6, "cas latency table," on page 13, indicates the operating frequencies at which each cas latency set- ting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 4: mode register definition diagram m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba1 and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 13 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm mode register definition notes: 1. for a burst length of two, a1?a i select the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2?a i select the four-data-element block; a0?a1 select the first access within the block. 3. for a burst length of eight, a3?a i select the eight-data-element block; a0?a2 select the first access within the block. 4. whenever a boundary of the block is reache d within a given sequence above, the follow- ing access wraps within the block. 5. i = 9 for 512mb i = 9, 11 for 1gb table 5: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 6: cas latency table speed allowable operating clock frequency (mhz) cl = 2 cl = 2.5 -335 75 f 133 75 f 166 -262 75 f 133 75 f 133 -26a 75 f 133 75 f 133 -265 75 f 100 75 f 133 -202 75 f 100 75 f 125 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 14 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm extended mode register figure 5: cas latency diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a12 each set to zero, and bits a0 ?a6 set to the desired values. a dll reset is initiated by issuing a mode register set co mmand with bits a7 and a9?a12 each set to zero, bit a8 set to one, and bits a0?a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode register command to select normal operating mode. all other combinations of values for a7?a12 are reserved for future use and/or test modes. test modes and reserved states sh ould not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and output drive strength. these functions are controlled via the bits shown in figure 6, "extended mode register definition diagram," on page 15. the extend ed mode register is programmed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register com- mand to the mode register (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded wh en all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any sub- sequent operation. violating either of thes e requirements could result in unspecified operation. ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 15 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm extended mode register dll enable/disable the dll must be enabled for normal operatio n. dll enable is required during power- up initialization and upon returning to norm al operation after having disabled the dll for the purpose of debug or evaluation. when the device exits self refresh mode, the dll is enabled automatically. any time the dll is enabled, 200 clock cycles with cke high must occur before a read command can be issued. figure 6: extended mode register definition diagram notes: 1. ba1 and ba0 (e14 and e13) must be ?0, 1? to select the extended mode register (vs. the base mode register). 2. qfc# is not supported. operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 e0 0 drive strength normal e1 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds 0 ? e2 2 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 16 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm commands commands table 7, commands truth table, and table 8, dm operation truth table, provide a gen- eral reference of available commands. for a more detailed description of commands and operations, refer to the 256mb or 512 mb ddr sdram component data sheets. notes: 1. deselect and nop are functionally interchangeable. 2. ba0?ba1 provide device bank addr ess and a0?a12 provide row address. 3. ba0?ba1 provide device bank address; a0?a 9 (512mb) or a0?a9, a11 (1gb) provide col- umn address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts wi th auto precharge disabled; th is command is undefined (and should not be us ed) for read bursts with auto precharge enabled and for write bursts. 5. a10 low: ba0?ba1 determine which device bank is precharged. a10 high: all device banks are precharged and ba0?ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addr essing; all inputs and i/os are ?don?t care? except for cke. 8. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 se lect extended mode register; other combina- tions of ba0?ba1 are reserved). a0?a12 provide the op-code to be written to the selected mode register. table 7: commands truth table cke is high for all commands shown except self refresh; all states and sequences not shown are illegal or reserved name (function) cs# ras# cas# we# addr notes deselect (nop) hx xx x 1 no operation (nop) lh hh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) l h l h bank/col 3 write (select bank and colu mn, and start write burst) l h l l bank/col 3 burst terminate lh hl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) ll lh x 6, 7 load mode register ll llop-code 8 table 8: dm operation truth table used to mask write data; provided co incident with the corresponding data name (function) dm dqs write enable lvalid write inhibit hx pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 17 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm absolute maximum ratings absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. voltage on v dd supply, relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v dd q supply, relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v ref and inputs, relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on i/o pins, relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd q +0.5v operating temperature t a (ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0c to + 70c storage temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +150c short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0ma table 9: dc electrical characteristics and operating conditions notes: 1?5, 14; notes appear on pages 22?26; 0c t a +70c parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 32, 36 i/o supply voltage v ddq 2.3 2.7 v 32, 36, 39 i/o reference voltage v ref 0.49 x vddq 0.51 x v dd q v6, 39 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 39 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il (dc) -0.3 v ref - 0.15 v 25 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) command/ address, ras#, cas#, we#, s#, cke i i -5 5 a 46 ck, ck# -10 10 dm -4 4 output leakage current (dqs are disabled; 0v v out v dd q) dq, dqs i oz -10 10 a 46 output levels high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 34 i ol 16.8 ? ma table 10: ac input operating conditions notes: 1?5, 14, 48; notes appear on pages 22?26; 0c t a +70c; v dd = v dd q = +2.5v 0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v 12, 25, 35 input low (logic 0) voltage v il ( ac )?v ref - 0.310 v 12, 25, 35 i/o reference voltage v ref ( ac ) 0.49 x v dd q0.51 x v dd qv 6 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 18 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm electrical specifications electrical specifications table 11: i dd specifications and conditions ? 512mb ddr sdram components only notes: 1?5, 8, 10, 12, 47; no tes appear on pages 22?26; 0c t a +70c; v dd = v dd q = +2.5v 0.2v max parameter/condition sym -335 -262 -26a/ -265 units notes operating current: one devi ce bank; acti ve-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and contro l inputs changing once every two clock cycles i dd 0 a 1,161 1,161 981 ma 20, 41 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 1,566 1,476 1,341 ma 20, 41 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 72 72 72 ma 21, 28, 43 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 900 810 810 ma 44 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 540 450 450 ma 21, 28, 43 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 1,080 900 900 ma operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 1,611 1,386 1,386 ma 20, 41 operating current: burst = 2; writes; continuous burst; one device bank active; address and co ntrol inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 1,611 1,386 1,386 ma 20 auto refresh current t refc = t rfc (min) i dd5 b 4,590 4,230 4,230 ma 20, 43 t refc = 7.8125s i dd5a b 108 108 108 ma 24, 43 self refresh current: cke 0.2v i dd6 b 72 72 72 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 a 3,726 3,186 3,186 ma 20, 42 note: a: value calculated as one module rank in this operating co ndition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all module ranks in this operating condition. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 19 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm electrical specifications table 12: i dd specifications an d conditions ? 1gb ddr sdram components only notes: 1?5, 8, 10, 12, 47; no tes appear on pages 22?26; 0c t a +70c; v dd = v dd q = +2.5v 0.2v max parameter/condition sym -335 -262 -26a/ -265 units notes operating current: one devi ce bank; acti ve-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd 0 a 1,215 1,215 1,080 ma 20, 41 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 1,485 1,485 1,350 ma 20, 41 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 90 90 90 ma 21, 28, 43 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 810 810 720 ma 44 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 630 630 540 ma 21, 28, 43 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 900 900 810 ma operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 1,530 1,530 1,350 ma 20, 41 operating current: burst = 2; writes; continuous burst; one device bank active; address and co ntrol inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 1,620 1,440 1,260 ma 20 auto refresh current t refc = t rfc (min) i dd5 b 5,220 5,220 5,040 ma 20, 43 t refc = 7.8125s i dd5a b 180 180 180 ma 24, 43 self refresh current: cke 0.2v i dd6 b 90 90 90 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd7 a 3,690 3,645 3,195 ma 20, 42 note: a: value calculated as one module rank in this operating co ndition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all module ranks in this operating condition. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 20 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm electrical specifications table 13: capacitance (512mb only) note: 11; notes appear on pages 22?26 parameter symbol min max units input/output capacitance: dq, dqs, dm c i0 810 pf input capacitance: command and address, s#, cke c i1 2.5 3.5 pf input capacitance: ck, ck# c i2 ? 4pf table 14: electrical characteristics and recommended ac operating conditions ddr sdram components only notes: 1?5, 12?15, 29, 48; no tes appear on pages 22?26; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -335 -262 -26a/-265 parameter symbol min max min max min max units notes access window of dqs from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 2.5 t ck (2.5) 6 13 7.5 13 7.5 13 ns 40, 45 cl = 2 t ck (2) 7.5 13 7.5/10 13 7.5/10 13 ns 40, 45 dq and dm input hold time relative to dqs t dh 0.45 0.5 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.35 0.5 0.5 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 +0.75 ns 16, 37 data-out low-impedance window from ck/ck# t lz -0.70 -0.75 -0.75 ns 16, 37 address and control input hold time (fast slew rate) t ih f 0.75 0.90 .90 ns 12 address and control input setup time (fast slew rate) t is f 0.75 0.90 .90 ns 12 address and control input hold time (slow slew rate) t ih s 0.80 1 1 ns 12 address and control input setup time (slow slew rate) t is s 0.80 1 1 ns 12 address and control input pulse width (for each input) t ipw 2.20 2.20 2.20 ns load mode register command cycle time t mrd 12 15 15 ns dq-dqs hold, dqs to firs t dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.50 0.75 0.75 ns active to precharge command t ras 42 120,000 40 120,000 40 120,000 ns 31, 48 active to read with auto precharge command t rap 15 15 20 ns pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 21 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm electrical specifications active to active/auto refresh command period t rc 60 60 65 ns auto refresh command period t rfc 75 75 75 ns 43 active to read or write delay t rcd 15 15 20 ns precharge command period t rp 15 15 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 38 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 38 active bank a to active bank b command t rrd 12 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 1 1 1 t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval t refc 70.3 70.3 70.3 s 21 average periodic refresh interval t refi 15.6 15.6 7.8 s 21 terminating voltage delay to v dd t vtd 0 0 0 ns exit self refresh to non-read command t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 t ck table 14: electrical characteristics and recomm ended ac operating conditions (continued) ddr sdram components only notes: 1?5, 12?15, 29, 48; no tes appear on pages 22?26; 0c t a +70c; v dd = v dd q = +2.5v 0.2v ac characteristics -335 -262 -26a/-265 parameter symbol min max min max min max units notes pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 22 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm notes notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for th e input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as th e signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ddq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2 for -2 62, and -26a, cl = 2.5 for-335 and -265 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialize d, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out ( dc ) = v ddq /2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. for slew rates less than 1 v/ns and greater th an or equal to 0.5 v/ns. if slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from 500 mv/ns, while t ih is unaffected. if slew rate exceeds 4.5 v/ns, functionality is uncertain. for -335, slew rates must be 0.5 v/ns. 13. the ck/ck# input reference level (for ti ming referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v ddq is recognized as low. 15. the output timing reference level, measured at the timing reference point indicated in note 3, is v tt . output (v out ) reference point 50 v tt 30pf pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 23 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm notes 16. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the don?t care state after completion of the postamble is that the dqs- driven signal should either be high, low, or high-z and that any signal transition within the input switching region must foll ow valid input requirements. if dqs transi- tions to high above v ih (dc) min, then it must not transition to low below v ih (dc) min prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measure- ments is the largest multiple of t ck that meets the maximum absolute value for t ras. 21. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. how- ever, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly porpor- tional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle vari ation of 45/55, beyond which functionality is uncertain. figure 7, derating data valid window (tqh - tdqsq), shows derating curves. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, co ntinue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec specifies ck and ck# input slew rate must be 1 v/ns (2 v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncertain. for -335, slew rates must be 0.5 v/ns. 28. v dd must not vary more than 4 percent if ck e is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the internal precharge command being issued. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 24 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm notes figure 7: derating data valid window ( t qh - t dqsq) 32. any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9v max, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2v min, whichever is more positive. however, the dc average cannot be below 2.3v minimum. 33. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum pro- cess, temperature and voltage will lie with in the outer bounding lines of the v-i curve of figure 8, "pull-down," on page 25. b. the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaran teed, to lie within the inner bounding lines of the v-i curve of figure 8, "pull-down," on page 25. c. the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, "pull-up," on page 25. d. the variation in driver pull-up current within nominal limits of voltage and tem- perature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, "pull-up," on page 25. e. the full variation in the ratio of the maximum to minimum pull-up and pull- down current should be between 0.71 and 1.4, for device drain-to-source volt- ages from 0.1v to 1.0v, and at th e same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drai n-to-source voltages from 0.1v to 1.0v. 34. the voltage levels used are derived from a minimum v dd level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly different voltage values. 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns -335 -262/-26a/-265 @ t ck = 10ns -262/-26a/-265 @ t ck = 7.5ns na pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 25 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm notes 35. v ih overshoot: v ih (max) = v ddq + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. v dd and v ddq must track each other. 37. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 38. t rpst end point and trpre begin point are no t referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst), or begins driving ( t rpre). 39. during initialization, v ddq , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v ddq are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. 40. the current micron part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 41. random addressing changing and 50 perc ent of data changing at every transfer. 42. random addressing changing and 100 perc ent of data changing at every transfer. 43. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each risi ng clock edge, until t ref later. figure 8: pull-down figure 9: pull-up 160 140 i out (ma) v out (v) nominal low minimum nominal high maximum 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) 0 -20 i out (ma) nominal low minimum nominal high maximum -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 v dd q - v out (v) pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 26 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm notes 44. i dd 2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 45. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles (before read commands). 46. leakage number reflects the worst case le akage possible through the module pin, not what each memory device contributes. 47. when an input signal is high or low, it is defined as a steady state logic high or low. 48. the -335 speed grade will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 27 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm initialization initialization to ensure device operation the dram mu st be initialized as described below: 1. simultaneously apply power to v dd and v dd q. 2. apply v ref and then v tt power. 3. assert and hold cke at a lvcmos logic low. 4. provide stable clock signals. 5. wait at least 200s. 6. bring cke high and provide at least one nop or deselect command. at this point the cke input changes from a lvcmos input to a sstl2 input only, and will remain a sstl_2 input unless a power cycle occurs. 7. perform a precharge all command. 8. wait at least t rp time, during which nop or deselect commands must be given. 9. using the lmr command program the extended mode register (e0 = 0 to enable the dll and e1 = 0 for normal drive or e1 = 1 for reduced drive, e2 through e n must be set to 0; where n = most significant bit). 10. wait at least t mrd time; only nop or deselect commands are allowed. 11. using the lmr command, program the mode register to set operating parameters and to reset the dll. at least 200 clock cy cles are required between a dll reset and any read command. 12. wait at least t mrd time; only nop or deselect commands are allowed. 13. issue a precharge all command. 14. wait at least t rp time; only nop or dese lect commands are allowed. 15. issue an auto refresh command (this may be moved prior to step 13). 16. wait at least t rfc time; only nop or deselect commands are allowed. 17. issue an auto refresh command (this may be moved prior to step 13). 18. wait at least t rfc time: only nop or deselect commands are allowed. 19. although not required by the micron device, jedec requires a lmr command to clear the dll bit (set m8 = 0). if a lmr command is issued the same operating parameters should be utilized as in step 11. 20. wait at least t mrd time; only nop or deselect commands are allowed. at this point the module is ready for any valid command. please note that 200 clock cycles must pass between step 11 (dll reset) and any read command. pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 28 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm initialization figure 10: initialization flow diagram v dd and v dd q ramp apply v ref and v tt cke must be lvcmos low apply stable clocks bring cke high with a nop command wait at least 200s precharge all assert nop or deselect for t rp time configure extended mode register configure load mode register and reset dll assert nop or deselect for t mrd time assert nop or deselect for t mrd time precharge all issue auto refresh command assert nop or deselect for t rfc time optional lmr command to clear dll bit assert nop or deselect for t mrd time dram is ready for any valid command step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 assert nop or deselect commands for t rfc issue auto refresh command assert nop or deselect for t rp time pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 29 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm register and pll specifications register and pll specifications notes: 1. the timing and sw itching specifications fo r the register listed above are critical for proper operation of ddr sdram registered dimms. th ese are meant to be a subset of the param- eters for the specific device us ed on the module. detailed in formation for this register is available in jedec standard jesd82. 2. data inputs must be low a minimum time of t act max, after reset# is taken high. 3. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact max, after reset# is taken low. 4. for data signal input slew rate 1 v/ns. 5. for data signal input slew rate 0.5 v/ns and < 1 v/ns. 6. ck, ck# signals input slew rate 1 v/ns. table 15: register timing requirements and switching characteristics note 1 register symbol paramerter condition 0c t a +70c v dd = 2.5v 0.2v units notes min max sstl (bit pattern by jesd82-3 or jesd82-4 f clock clock frequency - 200 mhz t pd clock to output time 30pf to gnd and 50 to v tt 1.1 2.8 ns t phl reset to output time - 5 ns t w pulse duration ck, ck# high or low 2.5 - ns t act differential inputs active time -22ns 2 t inact differential inputs inactive time -22ns 3 t su setup time, fast slew rate data before ck high, ck# low 0.75 - ns 4, 6 setup time, slow slew rate 0.9 - ns 5, 6 t h hold time, fast slew rate data after ck high, ck# low 0.75 - ns 4, 6 hold time, slow slew rate 0.9 - ns 5, 6 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 30 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm register and pll specifications notes: 1. the timing and switching specifications for the pll listed above are critical for proper operation of ddr sdram registered dimms. th ese are meant to be a subset of the param- eters for the specific device us ed on the module. detailed info rmation for this pll is avail- able in jedec standard jesd82. 2. the pll must be able to handle spread spectrum induced skew. 3. operating clock frequency indicates a range ov er which the pll must be able to lock, but in which it is not required to meet the other timing parameters. (used for low-speed sys- tem debug.) 4. stabilization time is the time required for the integrated pll ci rcuit to obtain phase lock of its feedback signal to its re ference signal after power up. 5. static phase offset do es not include jitter. 6. period jitter and half-period ji tter specifications are separate specifications that must be met independently of each other. 7. the output slew rate is de termined from the ibis model: table 16: pll clock driver timing requirements and switching characteristics note: 1 parameter symbol 0c t a +70c v dd = 2.5v 0.2v units notes min nominal max operating clock frequency f ck 60 - 170 mhz 2, 3 input duty cycle t dc 40 - 60 % stabilization time t stab - - 100 ms 4 cycle to cycle jitter t jit cc -75 - 75 ps static phase offset t ? -50 0 50 ps 5 output clock skew t sk o -- 100ps period jitter t jit per -75 - 75 ps 6 half-period jitter t jit hper -100 - 100 ps 6 input clock slew rate t ls i 1.0 - 4 v/ns output clock slew rate t ls o 1.0 - 2 v/ns 7 v dd /2 gnd v dd cdcv857 r=60 r=60 v ck v ck pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 31 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm temperature and air flow specifications temperature and air flow specifications figure 11: component case temperature vs. air flow notes: 1. micron technology, inc. recommends a minimum air flow of 1 meter/second (~197 lfm) across all modules. 2. the component case temperature measuremen ts shown above were obtained experimen- tally. the typical system to be used for expe rimental purposes is a dual-processor 600 mhz work station, fully loaded, with four compar able registered memory modules. case tem- peratures charted represent wo rst-case component locations on modules installed in the internal slots of the system. 3. temperature versus air speed data is obtain ed by performing experiments with the system motherboard removed from its case and mounted in a eiffel -type low air speed wind tun- nel. peripheral devices installed on the sy stem motherboard for testing are the proces- sor(s) and video card, all othe r peripheral devices are mounted outside of the wind tunnel test chamber. 4. the memory diagnosti c software used for determining worst-case component tempera- tures is a memory diag nostic software appl ication developed for in ternal use by micron technology, inc. 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 2.0 air flow (meters/sec) degrees celsius ambient temperature = 25o c t max - memory stress software t ave - 3d gaming software t ave - memory stress software minimum air flow pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 32 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect serial presence-detect spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figure 12, "data valid- ity," on page 32, and figure 13, "definition of start and stop," on page 33). spd start condition all commands are preceded by the start cond ition, which is a hi gh-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high tran- sition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (fig ure 14, "acknowledge response from receiver," on page 33). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both th e device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each sub- sequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop conditio n is generated by the master, the slave will continue to transmit data. if an acknowledge is not dete cted, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 12: data validity scl sda data stable data stable data change pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 33 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect figure 13: definition of start and stop figure 14: acknowledge response from receiver scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 34 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect figure 15: spd eeprom timing diagram table 17: eeprom device select code the most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 18: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 35 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect notes: 1. to avoid spurious start and stop condit ions, a minimum delay is placed between scl = 1 and the falling or ri sing edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/prog ram cycle. duri ng the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tor, and the eeprom does not respond to its slave address. table 19: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il -0.6 v ddspd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current: scl = sda = v dd - 0.3v; all other inputs = v dd or v ss i sb 1.6 4 a power supply current, read: sc l clock frequency = 100 khz i cc r 0.4 1 ma powr supply current, write: scl clock frequency = 100 khz i cc w 23ma table 20: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 36 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect table 21: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?dr iven to low?; notes appear on page 37 byte description entry (version) mt18vdvf6472d MT18VDVF12872D 0 number of spd bytes used by micron 128 80 80 1 total number of bytes in spd device 256 08 08 2 fundamental memory type sdram ddr 07 07 3 number of row addresses on assembly 13 0d 0d 4 number of column addresses on assembly 10 or 11 0a 0b 5 number of physical ranks on dimm 20202 6 module data width 72 48 48 7 module data width (continued) 00000 8 module voltage interface levels sstl 2.5v 04 04 9 sdram cycle time, t ck (cas latency = 2.5) (see note 1) 6ns (-335) 7ns (-262/-26a) 7.5ns (-265) 60 70 75 60 70 75 10 sdram access from clock, t ac (cas latency = 2.5) 0.7ns (-335) 0.75ns (-262/-26a/-265) 70 75 70 75 11 module configuration type ecc 02 02 12 refresh rate/type 7.81s/self 82 82 13 sdram device widt h (primary sdram) 80808 14 error-checking sdram data width 80808 15 minimum clock delay, back-to-back random column access 1 clock 01 01 16 burst lengths supported 2, 4, 8 0e 0e 17 number of banks on sdram device 40404 18 cas latencies supported 2, 2.5 0c 0c 19 cs latency 00101 20 we latency 10202 21 sdram module attributes reg./diff. clk/pll 26 26 22 sdram device attributes: general fast/concurrent ap c0 c0 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-335/-262/-26a) 10ns (-265) 75 a0 75 a0 24 sdram access from ck, t ac (cas latency = 2) 0.70ns (-335) 0.75ns (-262/-26a/-265) 70 75 70 75 25 sdram cycle time, t ck, (cas latency = 1.5) n/a 00 00 26 sdram access from ck, t ac, (cas latency = 1.5) n/a 00 00 27 minimum row pr echarge time, t rp 18ns (-335) 15ns (-262) 20ns (-26a/-265) 48 3c 50 48 3c 50 28 minimum row ac tive to row active, (rrd 12ns (-335) 15ns (-262/-26a/-265) 30 3c 30 3c 29 minimum ras# to cas# delay, t rcd 18ns (-335) 15ns (-262) 20ns (-26a/-265) 48 3c 50 48 3c 50 30 minimum ras# pulse width, t ras (see note 2) 42ns (-335) 45ns (-262/-26a/-265) 2a 2d 2a 2d 31 module rank density 256mb, 512mb 40 80 32 address and command setup time, t is (see note 3) 0.80ns (-335) 1ns (262/-26a/-265) 80 a0 80 a0 pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 37 ?2003, 2004, 2005 micron technology, inc. all rights reserved. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm serial presence-detect notes: 1. value for -26a t ck set to 7ns (0x70) for optimum bios compatibility. actual device specifi- cation vaule is 7.5ns. 2. the value of t ras used for -26a/-265 modules is calculated from t rc - t rp. actual device specification value is 40 ns. 3. the jedec spd specification allows fast or slow slew rate values for these bytes. the worst- case (slow slew rate) value is repesented here . systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 33 address and command hold time, t ih (see note 3) 0.80ns (-335) 1ns (-262/-26a/-265) 80 a0 80 a0 34 data/data mask input setup time, t ds 0.45ns (-335) 0.50ns (-262/-26a/-265) 45 50 45 50 35 data/data mask input hold time, t dh 0.45ns (-335) 0.50ns (-262/-26a/-265) 45 50 45 50 36-40 reserved 00 00 41 minimum active auto refresh time t rc 60ns (-335/-262) 65ns (-26a/-265) 3c 41 3c 41 42 minimum auto refre sh to active/ auto refresh command period, t rfc 72ns (-335) 75ns (-262/-26a/-265) 48 4b 48 4b 43 sdram device max cycle time t ck max 12ns (-335) 13ns (-262/-26a/-265) 30 34 30 34 44 sdram device max dqs-dq skew time, t dqsq 0.40ns (-335) 0.5ns (-262/-26a/-265) 28 32 28 32 45 sdram device max read da ta hold skew factor, t qhs 0.50ns (-335) 0.75ns (-262/-26a/-265) 50 75 50 75 46 reserved 00 00 47 dimm height 11 11 48?61 reserved 00 00 62 spd revision release 1.0 10 10 63 checksum for bytes 0?62 -335 -262 -26a -265 46 e3 10 40 87 24 51 81 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff 72 manufacturing location 01?12 01?0c 01?0c 73-90 module part number (ascii) variable data variable data 91 pcb identification code 1-9 01-09 01-09 92 identification code (continued) 00000 93 year of manufacture in bcd variable data variable data 94 week of manufacture in bcd variable data variable data 95-98 module serial number variable data variable data 99-127 manufacturer-specific data (rsvd) ?? table 21: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?dr iven to low?; notes appear on page 37 byte description entry (version) mt18vdvf6472d MT18VDVF12872D ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 512mb, 1gb: (x72, dr) 184-pin ddr vlp rdimm module dimensions pdf: 09005aef81c73825/source: 09005aef81c73837 micron technology, inc., reserves the right to change products or specifications without notice. dvf18c64_128x72d_2.fm - rev. a 8/05 en 38 ?2003, 2004, 2005 micron technology, inc. all rights reserved. module dimensions all dimensions in inches (millimeters) or typical where noted. figure 16: 184-pin vlp rdimm dimensions data sheet designation released (no mark): this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. max min 0.725 (18.42) 0.715 (18.1 6 ) pin 1 0.098 (2.50) d (2x) 0.091 (2.30) typ. 0.250 ( 6 .35) typ. 4.750 (120. 6 5) typ. 0.050 (1.27) typ. 0.091 (2.30) typ. 0.040 (1.02) typ. 0.079 (2.00) r (4x) 0.035 (0.90) r pin 92 front view 5.25 6 (133.50) 5.244 (133.20) 2.55 ( 6 4.77) typ. 1.95 (49.53) typ. 0.394 (10.00) typ. ba c k view pin 184 pin 93 0.054 (1.37) 0.04 6 (1.17) 0.157 (3.99) max u11 u1 u2 u3 u4 u5 u 6 u7 u8 u9 u10 u11 u1 6 u17 u12 u13 u14 u15 u18 u19 u20 u21 u22 |
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